Non-volatile two transistor semiconductor memory cell and method for producing the same

ABSTRACT

The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions ( 2 ) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate ( 1 ). The memory transistor (ST) has a first insulation layer ( 3 ), a charge storage layer ( 4 ), a second insulation layer ( 5 ) and a memory transistor control layer ( 6 ), while the selection transistor (AT) has a first insulation layer ( 3 ′) and a selection transistor control layer ( 4* ). By using different materials for the charge storage layer ( 4 ) and the selection transistor control layer ( 4* ), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

The present invention relates to a nonvolatile two-transistorsemiconductor memory cell and an associated method for fabricating it,and in particular to a nonvolatile semiconductor memory cell having amemory transistor and a selection transistor connected thereto.

FIG. 1 shows a simplified sectional view of such a conventionalnonvolatile two-transistor semiconductor memory cell, in which case, ina semiconductor substrate 1, which is p⁻-doped, for example, a selectiontransistor AT and a memory transistor ST are formed and are connected toone another via a common source/drain region 2.

The memory transistor ST usually comprises an insulating tunnel oxidelayer 3, a conductive floating gate layer 4, an insulating dielectriclayer 5 and a conductive control gate layer 6. For storing information,charges are introduced from the semiconductor substrate 1 into thefloating gate layer 4. Examples of methods for introducing the chargesinto the floating gate layer 4 are injection of hot charge carriers andFowler-Nordheim tunnelling.

For the selection or driving of the actual memory transistor ST, thetwo-transistor semiconductor memory cell furthermore has a selectiontransistor AT which, as field-effect transistor, essentially has a gateoxide layer 3′ and a control gate layer 4 lying above the latter. Thefloating gate layer of the memory transistor and the control gate layerof the selection transistor are usually composed of the same material,such as e.g. polysilicon, which is n⁺-doped, for example.

In the case of such nonvolatile two-transistor semiconductor memorycells, the charge retention properties, in particular, are of greaterimportance for the use and the reliability. Said charge retentionproperties are usually limited by (anomalous) loss of charge resultingfrom leakage phenomena. Said loss of charge takes place for example onaccount of traps or imperfections within the tunnel oxide 3, atunnelling mechanism being assisted by said imperfections or traps (trapassisted tunnelling). In order to avoid such leakage currents or inorder to improve the charge retention properties, the layer thicknessesfor the tunnel oxide layer 3 and/or the dielectric layer 5 are usuallyincreased, as a result of which, however, the electrical properties ofthe memory cell deteriorate and it is necessary to raise in particularthe operating voltages for reading from, writing to and/or erasing thememory cell.

Therefore, the invention is based on the object of providing anonvolatile two-transistor semiconductor memory cell and an associatedfabrication method which have improved charge retention properties.

According to the invention, this object is achieved by means of thefeatures of Patent claim 1 with regard to the memory cell and by meansof the measures of Patent claim 8 with regard to the method.

In particular by virtue of the different configuration of the chargestorage layer in the memory transistor and the selection transistorcontrol layer in the selection transistor for the independentoptimization of the associated threshold voltages, it is possible torealize an improvement in the charge retention properties in the memorytransistor without impairing the electrical properties of the memorycell.

The selection transistor control layer (4*) and the charge storage layer(4) preferably have a different material or, in particular given thesame semiconductor material, a different doping. In this way, a fieldreduction and thus an improvement in the charge retention can beeffected in a targeted manner in the memory transistor, while theselection transistor has an essentially unchanged threshold voltage.

A semiconductor substrate with increased doping is preferably used, theselection transistor control layer and the charge storage layer having asemiconductor material with different doping. As a result, it ispossible to reduce the electric fields in the memory transistor and thusa leakage current based on tunnelling (caused e.g. by imperfections(traps)), since this tunnelling current is exponentially dependent onthe electric field. On the other hand, the resultant threshold voltageshift is compensated for by an adaptation of the work functions in theselection transistor control layer by means of an opposite doping, as aresult of which the absolute threshold voltage of the selectiontransistor AT is reduced and the read current through the entire cell isthus increased. This in turn allows simpler evaluation circuits on thechip.

As an alternative to increasing the dopant concentration in thesubstrate, it is also possible only or additionally to dope the channelregion or a surface of the substrate more heavily. Furthermore, as analternative to the entire doping of the substrate or to the surfacedoping, it is also possible to use an increased well doping in order tomodify the threshold voltage.

With regard to the method, a first insulation layer, an electricallyconductive semiconductor layer, a second insulation layer and a furtherelectrically conductive layer are formed, preferably both for theselection transistor and for the memory transistor, and patterned insuch a way as to produce the two transistors with source and drainregions lying in between in the semiconductor substrate. In this case,an opposite doping is alternatively or additionally to be used only forthe electrically conductive semiconductor layer of the selectiontransistor, in order to reduce the threshold voltage. In this way, anonvolatile two-transistor semiconductor memory cell having improvedcharge retention properties can be fabricated in a particularlycost-effective manner.

Further advantageous refinements of the invention are characterized inthe further subclaims.

The invention is described in more detail below using an exemplaryembodiment with reference to the drawing.

In the figures:

FIG. 1 shows a simplified sectional view of a conventional nonvolatiletwo-transistor semiconductor memory cell;

FIG. 2 shows a simplified sectional view of a nonvolatile two-transistorsemiconductor memory cell according to the invention;

FIGS. 3A to 3D shows simplified sectional views for illustratingessential fabrication steps for the nonvolatile two-transistorsemiconductor memory cell according to the invention;

FIGS. 4 a and 4B show simplified graphical representations forillustrating a dependence of the threshold voltages on time on accountof charge losses; and

FIGS. 5A to 5C show simplified graphical representations forillustrating the effects of a change in the work function on thethreshold voltages in the selection transistor and memory transistor.

FIG. 2 shows a simplified sectional view of a nonvolatile two-transistorsemiconductor memory cell in accordance with the present invention,identical reference symbols designating layers identical or similar tothose in FIG. 1.

In accordance with FIG. 2, a selection transistor AT and a memorytransistor ST which are connected to one another via a commonsource/drain region 2 are formed in a substrate 1, which is composed ofa p-doped silicon semiconductor material, by way of example. The memorytransistor ST has a first memory transistor insulation layer 3, whichpreferably has a tunnel oxide layer TOX and has a thickness ofapproximately 10 nm. A charge storage layer 4, which has an n⁺-dopedpolysilicon layer, by way of example, is situated at the surface of saidfirst memory transistor insulation layer 3, which comprises a thermallyformed SiO₂ layer, by way of example. Arranged above said layer 4 is asecond memory transistor insulation layer 5, which insulates the chargestorage layer 4 from a memory transistor control layer 6 arranged aboveit. The memory transistor control layer 6 may likewise have n⁺-dopedpolysilicon, by way of example, and essentially represents a word lineof the memory cell. The second memory transistor insulation layer 5 isalso referred to as interpoly dielectric and may have an ONO layersequence (oxide-nitride-oxide), by way of example.

For its part, the selection transistor AT comprises a first selectiontransistor insulation layer 3′ at the surface of the substrate 1 orchannel region lying between the source and drain regions 2, and aselection transistor control layer 4*. The selection transistorinsulation layer 3′ preferably comprises a gate oxide layer GOX. Theselection transistor control layer 4* likewise comprises an electricallyconductive layer and, by way of example, a p⁺-doped polysilicon layer.

The essential difference of the memory cell according to the inventionresults, then, from the modified doping of the substrate and theresultant modified natural threshold voltages in combination with thechoice of different materials or different dopings for the chargestorage layer 4 and the selection transistor control layer 4*. Anincreased threshold voltage of the memory transistor ST is obtained onaccount of an increased doping of the substrate 1 from p⁻ to p or p⁺with dopings remaining the same for the charge storage layer 4 and thememory transistor control layer 6. As is described in detail below, thisadaptation of the threshold voltage in the memory transistor ST yieldsthe possibility of optimizing the charge retention properties. On theother hand, in the selection transistor AT, a reduction of the thresholdvoltage is obtained by means of an opposite doping to the charge storagelayer 4. More precisely, the p⁺-type doping of the selection transistorcontrol layer 4* compensates for the increase in the threshold voltagethereof, as a result of which essentially a lowered threshold voltage isproduced in the selection transistor and an evaluation circuit (notillustrated) for evaluating the memory cell can thus be realized insimpler fashion.

Accordingly, what is essential to the present concept is that, in thememory transistor ST, the threshold voltage can be optimized with regardto charge retention by way of the substrate, well and/or channel dopingand that the resulting disadvantages for the selection transistor can becompensated for by means of an opposite doping to the charge storagelayer. As a result, it is possible to reduce the electric fieldsresponsible for tunnelling in the memory transistor, thereby producingan improved charge retention property, the electrical properties of thecell remaining unchanged with regard to external circuitry since thisthreshold shift is compensated for again in the selection transistor AT.

Although an identical material (polysilicon) with a differentconfiguration (doping) has been used above, the same effect is alsoobtained when using different materials (different metals,semiconductors, etc.) for the charge storage layer 4 and the selectiontransistor control layer 4*.

The relationships described above are explained in detail below, butfirst a description is given of one possible method for fabricating sucha nonvolatile two-transistor semiconductor memory cell.

FIGS. 3A to 3D show simplified sectional views of illustrating essentialfabrication steps for the nonvolatile two-transistor semiconductormemory cell according to the invention, identical reference symbolsdesignating identical or similar layers and a repeated description beingdispensed with below.

In accordance with FIG. 3A, firstly a first insulation layer 3 is formedboth in a selection transistor region and in a memory transistor regionon a substrate 1, which has, by way of example, a silicon semiconductorsubstrate with an increased p-type doping. Said first insulation layer 3or 3′ is composed of a thermally formed silicon dioxide, by way ofexample. A positive effect of a first insulation layer or gate oxidelayer 3′ of sufficient thickness in the selection transistor region isthe avoidance of a dopant, for example boron, penetration into thesubstrate 1 which can result from a subsequent doping.

An electrically conductive semiconductor layer 4 or 4* (e.g. polysiliconlayer) is subsequently formed at the surface, this layer having adoping, such as e.g. an n⁺-type doping, which is opposite to the dopingof the substrate 1 for example as a result of a mask in the region ofthe memory transistor ST. By contrast, by means of a masking, forexample, the electrically conductive semiconductor layer 4* can be dopedwith a doping of the first conduction type, such as e.g. a p⁺-typedoping, which is identical to the substrate 1. In this way, theabove-described threshold voltages are already set differently in thedifferent regions, a threshold voltage in the selection transistorregion preferably being set in such a way that there is no differencefrom the selection transistor of a conventional nonvolatiletwo-transistor semiconductor memory cell, as a result of which e.g.already existing evaluation circuits or concepts can be adopted withoutany difficulty.

As an alternative, however, a superposed doping can also take place, inwhich case, by way of example, firstly an n-doped electricallyconductive layer is deposited both for the selection transistor regionand for the memory transistor region (for example in-situ doped) and acounterdoping is subsequently effected for the selection transistorregion by means of a masked implantation, by way of example. Inprinciple, the first whole-area doping can also be implemented by awhole-area implantation or some other doping.

The differently doped polylayers 4 and 4* are preferably fabricated bymeans of conventional phototechnology and implantation, in which caseone of these can be effected over the whole area and just the second ismasked by means of phototechnology, by way of example. Consequently, anovercompensation of the first doping is effected in the course of thisdoping. Boron is usually used for the p-type doping of the electricallyconductive semiconductor layer 4* in the selection transistor region,while a phosphorous or arsenic doping is usually carried out for then-type doping in the memory transistor region.

In accordance with FIG. 3B, in a subsequent step, a second insulationlayer 5 is formed at the surface of the electrically conductivesemiconductor layer 4 or 4*, in which case this must be formed at leastin the memory transistor region. This second insulation layer 5 isusually referred to as interpoly dielectric and may have an ONO layersequence, by way of example, as a result of which particularly goodinsulation properties in conjunction with good capacitive coupling canbe realized and, in particular, leakage currents to a subsequentlyformed further electrically conductive layer 6 are prevented. Thefurther electrically conductive layer 6 in turn comprises for example ann⁺-doped polysilicon layer which is deposited or grown by a conventionalmethod.

Finally, a mask layer 7 is formed at the surface of at least the furtherelectrically conductive layer 6 in the memory transistor region ST andthe electrically conductive semiconductor layer in the selectiontransistor region AT and patterned, it being possible to use aconventional hard mask layer, by way of example.

In accordance with FIG. 3C, firstly the further electrically conductivelayer 6 is then partly removed using the patterned mask layer 7, as aresult of which firstly the word lines of the memory transistors ST and,moreover, by further removing the layers down to the electricallyconductive semiconductor layer 4 or 4*, also the lines of the selectiongates of the selection transistors are obtained. A respectivelyavailable standard etching method can be used for removing these layers4 or 4*, 5 and 6, anisotropic etching methods being appropriate, inparticular, which act selectively with respect to the first insulationlayer 3, 3′ and with respect to the mask layer 7.

In accordance with FIG. 3D, in a final fabrication step, a self-aligningimplantation I is carried out in order to realize the source/drainregions 2, an n⁺-type doping by means of phosphorous or arsenic, forexample, being effected in order to fabricate an NMOS transistor.Further fabrication steps for completing the two-transistorsemiconductor memory cell are not described below since they aregenerally known.

In this case, the layers 5, 6 and 7 that are not required for theselection transistor AT remain unconnected or can be removed in asubsequent method step. In this way, a nonvolatile two-transistorsemiconductor memory cell with improved charge retention properties isobtained which can be fabricated in a particularly simple manner.

In order to illustrate the method of operation of the memory cellaccording to the invention, the influences of a threshold voltage in thememory transistor on the charge retention properties are described withreference to FIGS. 4A and 4B.

FIG. 4A shows a graphical representation of the critical thresholdvoltages in a memory cell and their time dependence if the memory cellexhibits (anomalous) charge loss effects.

In accordance with FIG. 4A, V_(th,uv) represents a threshold voltage ofthe memory transistor ST in an uncharged state (e.g. after a UVerasure). The branches V_(th,ST) show the threshold voltage of thememory transistor ST in the charged state and the transient profile ofthe threshold voltage through to the so-called uncharged state, in whichthere are no charges whatsoever in the charge-storing layer 4. Thisdischarge essentially results from leakage currents brought about bye.g. trap assisted tunnelling.

V_(th,A) represents a threshold voltage of an evaluation circuit that isusually required for the memory cell, which may be more or less high orfine. What holds true in principle, however, is that an associatedevaluation circuit can be produced particularly simply andcost-effectively the higher said voltage V_(th,A) is. On the other hand,FIG. 4A shows that the higher this threshold voltage V_(th,A) is, theearlier an instant t_(max) is reached at which a stored bit is onlyidentified erroneously by the evaluation circuit.

The present invention now effects a raising of the threshold voltageV_(th,UV) of the memory transistor ST in the uncharged state and of itsassociated discharge curves V_(th,ST) by means of, for example, theabove-described increase in a substrate doping, a channel region doping,and/or a well doping. The ideal curve illustrated in FIG. 4B is obtainedas a result of this raising of the threshold voltage V_(th,UV), animproved charge retention property being obtained since the thresholdvoltage V_(th,A) of the evaluation circuit coincides with the thresholdvoltage V_(th,UV) of the memory transistor.

FIGS. 5A to 5C show graphical representations for further illustrationof the threshold changes according to the invention on account of thechanges in the substrate doping or the opposite gate doping of theselection transistor (different configuration of charge storage layerand selection transistor control layer).

FIG. 5A shows a graphical representation of the threshold voltagesV_(th) for a selection transistor AT and a memory transistor ST, adifference in the respective threshold voltages already being producedon account of coupling effects of the different insulation layers GOXand TOX and of the layer 5 in the respective regions. As a rule, thememory transistor ST formed in the same substrate 1 has a higherthreshold value V_(th) than the associated selection transistor AT.

The effect of increasing the substrate doping is now described inaccordance with FIG. 5B, both threshold voltages being raised equally asa result of the increased doping in the substrate 1, as a result of anincreased well doping and/or an increased surface doping. In this way,although the improved charge retention properties in the memorytransistor ST in FIG. 4B are already obtained, the electrical propertiesof the memory cell are significantly impaired in particular on accountof the increased threshold voltages in the selection transistor.

Accordingly, a correction of the threshold raising in the selectiontransistor AT is effected in accordance with FIG. 5C, which isessentially effected by increasing the work function for electrons inthe control layer by means of an opposite p-type doping, by way ofexample. This change in the work function only in the selectiontransistor AT accordingly forces back the threshold voltage V_(th) inthis region again, as a result of which a threshold voltage similar tothe initial state and, consequently, similarly good electricalproperties of the memory cell are obtained. In this way, the chargeretention properties in a two-transistor semiconductor memory cell canbe significantly improved without influencing the electrical propertiesor a required evaluation circuit.

The invention has been described above using an NMOS memory cell.However, it is not restricted thereto and encompasses PMOS or acombination of PMOS and NMOS cells or transistors in the same way. Inthe same way, the invention is not restricted to silicon semiconductormaterials, but rather encompasses all further semiconductor materialswhich can be used to alter a threshold voltage in a targeted manner inorder to improve the charge retention properties. In the same way, forthe charge storage layer, the memory transistor control layer and theselection transistor control layer, it is possible to use not just asemiconductor material, but rather, in the same way, an alternativematerial such as e.g. metals.

List of Reference Symbols

-   1 Substrate-   2 Source/drain regions-   3, 3′ First insulation layer-   4 Charge storage layer-   4* Selection transistor control layer-   5 Second insulation layer-   6 Memory transistor control layer-   7 Mask layer-   AT Selection transistor-   ST Memory transistor-   V_(th,A) Threshold voltage of the evaluation circuit-   V_(th,UV) Threshold voltage of the memory transistor in the    uncharged state-   V_(th,ST) Threshold voltage of the memory transistor in the charged    state

1. Nonvolatile two-transistor semiconductor memory cell having a memorytransistor (ST) having a predetermined threshold voltage, which has asource and drain region (2) with a channel region lying in between in asubstrate (1), a first memory transistor insulation layer (3), a chargestorage layer (4), a second memory transistor insulation layer (5) and amemory transistor control layer (6) being formed at the surface of thechannel region; and a selection transistor (AT) having a predeterminedthreshold voltage, which has a source and drain region (2) with achannel region lying in between in the substrate (1), a first selectiontransistor insulation layer (3′) and a selection transistor controllayer (4*) being formed at the surface of the channel region,characterized in that for the independent optimization of the thresholdvoltages (V_(th)) of the memory transistor (ST) and of the selectiontransistor (AT), the selection transistor control layer (4*) is formeddifferently from the charge storage layer (4).
 2. Nonvolatiletwo-transistor semiconductor memory cell according to Patent claim 1,characterized in that the selection transistor control layer (4*) andthe charge storage layer (4) have a different material and/or adifferent doping.
 3. Nonvolatile two-transistor semiconductor memorycell according to Patent claim 1 or 2, characterized in that thesubstrate (1) has a semiconductor material with a doping of the firstconduction type (p), the selection transistor control layer (4*) has asemiconductor material with a doping of the first conduction type (p),and the charge storage layer (4) has a semiconductor material with adoping of the second conduction type (n), which doping is opposite tothe first conduction type.
 4. Nonvolatile two-transistor semiconductormemory cell according to one of Patent claims 1 to 3, characterized inthat the dopant concentration of the first conduction type (p) isincreased in the substrate (1), the channel regions or a well region. 5.Nonvolatile two-transistor semiconductor memory cell according to one ofPatent claims 1 to 4, characterized in that the first memory transistorinsulation layer (3) and the first selection transistor insulation (3′)have an SiO₂ layer.
 6. Nonvolatile two-transistor semiconductor memorycell according to one of Patent claims 1 to 5, characterized in that thecharge storage layer (4) and the selection transistor control layer (4*)have a polysilicon layer and/or a metallic layer.
 7. Nonvolatiletwo-transistor semiconductor memory cell according to one of Patentclaims 1 to 6, characterized in that the memory transistor (ST) and theselection transistor (AT) represent an NMOS and/or a PMOS transistor. 8.Method for fabricating a nonvolatile two-transistor semiconductor memorycell having the following steps: a) formation of a first insulationlayer (3, 3′) for a selection transistor (AT) and a memory transistor(ST) on a semiconductor substrate (1), which has a doping of the firstconduction type (p); b) formation of a semiconductor layer (4) at thesurface of the first insulation layer (3, 3′), which has a doping of thefirst conduction type (p) in a region of the selection transistor (AT)and a doping of the second conduction type (n), which doping is oppositeto the first conduction type, in a region of the memory transistor (ST);c) formation of a second insulation layer (5) at the surface of theelectrically conductive semiconductor layer (4) at least in the regionof the memory transistor (ST); d) formation of a further electricallyconductive layer (6) at the surface of the second insulation layer (5)at least in the region of the memory transistor (ST); e) formation andpatterning of a mask layer (7); f) formation of layer stacks in theregion of the selection transistor (AT) and of the memory transistor(ST) using the patterned mask layer (7); and g) formation of source anddrain regions (2) with a doping of the second conduction type (n) usingthe layer stack as mask.
 9. Method according to Patent claim 8,characterized in that, in step a), a semiconductor substrate (1) withincreased basic doping, well doping and/or surface doping of the firstconduction type (p) is used.
 10. Method according to either of Patentclaims 8 or 9, characterized in that, in step a), a tunnel oxide layer(TOX) is formed in the region of the memory transistor (ST) and a gateoxide layer (GOX) is formed in the region of the selection transistor(AT).
 11. Method according to one of patent claims 9 to 10,characterized in that, in step b), a polysilicon layer is deposited andthe different doping in the region of the selection transistor (AT) andof the memory transistor (ST) is effected by a masked implantation. 12.Method according to one of Patent claims 9 to 11, characterized in that,in step c), an ONO layer sequence is formed.
 13. Method according to oneof Patent claims 9 to 12, characterized in that, in step d), a furtherpolysilicon layer is deposited, which has a doping of the secondconduction type (n).
 14. Method according to one of Patent claims 9 to13, characterized in that, in step e), a hard mask layer is formed. 15.Method according to one of Patent claims 9 to 14, characterized in that,in step f), an anisotropic etching method is carried out.
 16. Methodaccording to one of Patent claims 9 to 15, characterized in that, instep g), an ion implantation (I) is carried out.